Titolo:  Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
Data di pubblicazione:  2017
Autori: 
Autori:  Sau, C; Palumbo, F; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, P; Raffo, L
Numero degli autori:  8
Lingua:  Inglese
Presenza coautori internazionali: 
Rivista:  IEEE EMBEDDED SYSTEMS LETTERS
Volume:  9
Fascicolo:  3
Pagina iniziale:  65
Pagina finale:  68
Numero di pagine:  4
Digital Object Identifier (DOI):  http://dx.doi.org/10.1109/LES.2017.2703585
Codice identificativo Scopus:  2-s2.0-85029027111
Codice identificativo ISI:  WOS:000409103400004
URL:  http://www.ieee.org
http://ieeexplore.ieee.org/document/7932478/
Abstract:  Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.
Parole chiave:  Embedded applications; field programmable gate array (FPGA); FIR filters; low power architectures; low power design; reconfigurable computing; runtime reconfiguration; signal processing; Control and Systems Engineering; Computer Science (all)
Tipologia: 1.1 Articolo in rivista

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