Titolo:  Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
Data di pubblicazione:  2014
Autori:  Sau C; Raffo L; Palumbo F; Bezati E; Casale-Brunet S; Mattavelli M
Presenza coautori internazionali: 
Titolo del libro:  Proceedings - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014
ISBN:  978-147993770-7
Editore:  IEEE
Tutti i curatori:  Galuzzi C; Veidenbaum AV
Sezione:  contributo
Pagina iniziale:  59
Pagina finale:  66
Numero di pagine:  8
Digital Object Identifier (DOI):  http://dx.doi.org/10.1109/SAMOS.2014.6893195
Codice identificativo Scopus:  2-s2.0-84907895849
Codice identificativo ISI:  WOS:000361019300008
URL:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6893195
Nome del convegno:  14th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2014
Periodo del convegno:  14-17 July 2014
Luogo del convegno:  Samos, Greece
Abstract:  Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, system configuration along with resource management and mapping are challenging, especially when runtime adaptivity is required. In order to address these issues, the Reconfigurable Video Coding Group within the MPEG group has developed the MPEG RMC standards ISO/IEC 23001-4 and 23002-4, based on the dataflow Model of Computation. In this paper, we propose an integrated design flow, leveraging on Xronos, TURNUS, and the Multi-Dataflow Composer tool, capable of automatic synthesis and mapping of reconfigurable systems. In particular, an RVC MPEG-4 SP decoder and the RVC Intra MPEG-4 SP decoder have been implemented on the same coarse-grained reconfigurable platform, targeting a Xilinx Virtex 5 330 FPGA board. Results confirmed the potentiality of the approach, capable of completely preserving the single decoders functionality and of providing, in addition, considerable power/area benefits with respect to the parallel implementation of the considered decoders on the same platform.
Tipologia: 4.1 Contributo in Atti di convegno

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