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Title Issue Date Author(s) Journal Publisher
Networks on Chips: A Synthesis Perspective 2005 F. ANGIOLINI; P. MELONI; D. BERTOZZI; L. BENINI; CARTA S.M.; L. RAFFO
Routing Aware Switch Hardware Customization for Networks on Chips 2006 MELONI P; MURALI S; CARTA S; CAMPLANI M; RAFFO L; DE MICHELI G
Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness 2006 F.ANGIOLINI; P.MELONI; CARTA S.M.; L. BENINI; L.RAFFO
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems-on-Chips 2006 MURALI S; MELONI P; ANGIOLINI F; ATIENZA D; CARTA S; BENINI L; DE MICHELI G; RAFFO L
Area and Power Modeling Methodologies for Networks-on-Chip 2006 P. MELONI; CARTA S.M.; R. ARGIOLAS; L. RAFFO; F. ANGIOLINI
Design Application-Specific Networks on Chips with Floorplan Information 2006 MURALI S; MELONI P; ANGIOLINI F; ATIENZA D; CARTA S; BENINI L; DE MICHELI G; RAFFO L
On the impact of serializatioin on the cache performances in Network-on-Chip based MPSoCs 2007 MELONI P; BUSONERA G; CARTA SM; RAFFO L
NoC Design and Implementation in 65nm Technology 2007 PULLINI A; ANGIOLINI F; MELONI P; ATIENZA D; MURALI S; RAFFO L
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs 2007 Angiolini F; Meloni P; Carta S; Raffo L; Benini L IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Synthesis of predictable networks-on-chip-based interconnect Architectures for chip multiprocessors 2007 MURALI S; ATIENZA D; MELONI P; CARTA S; BENINI L; DE MICHELI G; RAFFO L IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Optimizing the serialization factor in Networks-on-Chip: a case of study 2007 BUSONERA G; MELONI P; CARTA SM; RAFFO L
Area and Power Modeling for Networks-on-Chip with Layout Awareness 2007 MELONI P; LOI I; ANGIOLINI F; CARTA S; BARBARO M; RAFFO L; BENINI L VLSI DESIGN
Designing Routing and Message-Dependent Deadlock Free Networks on Chips 2008 MURALI S; MELONI P; ANGIOLINI F; ATIENZA D; CARTA SM; BENINI L; DE MICHELI G; RAFFO L
Methods for hardware reduction and overall performance improvement in communication systems 2008 Carta S M; Meloni P; De Micheli G; Raffo L
Design and optimization techniques for VLSI Network on Chip architectures 28-Mar-2008 Università degli Studi di Cagliari
An FPGA Research Environment for Rapid MPSoC Exploration 2009 SECCHI S; MELONI P; RAFFO L
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures 2010 SECCHI S; MELONI P; RAFFO L
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures 2010 MELONI P; SECCHI S; RAFFO L IEEE EMBEDDED SYSTEMS LETTERS
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper 2010 MELONI P; SECCHI S; RAFFO L
Enabling fast ASIP design space exploration: An FPGA-based runtime reconfigurable prototyper 2012 Meloni P; Pomata S; Tuveri G; Secchi S; Raffo L; Lindwer M VLSI DESIGN

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