Showing results 1 to 20 of 53
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Title Issue Date Author(s) Journal Publisher
Non-Exclusive Dual-Mode Approach for NoC Designs 2008 Palumbo F; Secchi S; Pani D; Raffo L
A Novel Non-Exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs 2008 Palumbo F; Secchi S; Pani D; Raffo L Springer
A surface tension and coalescence model for dynamic distributed resources allocation in Massively Parallel Processors on-Chip 2008 Palumbo F; Pani D; Raffo L; Secchi S Springer-Verlag
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching 2008 Secchi S; Palumbo F; Pani D; Raffo L IEEE COMPUTER SOCIETY
sysCgrid – SystemC grid simulation framework 2009 Palumbo F; Pani D; Raffo L
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations 2010 Pani D; Palumbo F; Raffo L INTERNATIONAL JOURNAL OF HIGH PERFORMANCE SYSTEMS ARCHITECTURE
Impact of half-duplex and full-duplex DMA Implementations on NoC performance 2010 Palumbo F; Pani D; Pilia A; Raffo L IEEE COMPUTER SOCIETY
Towards self-adaptive networks on chip for massively parallel processors: Multilevel quality of service programmability 2011 Palumbo F; Pani D; Deidda A; Raffo L ACM Digital Library
Hybrid switching techniques for heterogeneous traffic support in multi-processors system on chip and massively parallel processors 2011 Palumbo F; Pani D; Raffo L Nova Science Publishers, Inc.
The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer 2011 Palumbo F; Carta N; Raffo L IEEE
Coarse-Grained Reconfigurable Approach for Multi-Dataflow Systems 2011 Carta N; Palumbo F; Raffo L
A nature-inspired adaptive floating-point coprocessing system 2012 Sau C; Pani D; Palumbo F; Raffo L IEEE
Concurrent hybrid switching for massively parallel systems-on-chip: The CYBER architecture 2012 Palumbo F; Pani D; Congiu A; Raffo L ACM
Design IP Faster: Introducing the C~ High-Level Language 2012 Wipliez M; Siret N; Carta N; Palumbo F; Raffo L
Multi-purpose systems: A novel dataflow-based generation and mapping strategy 2012 Nezan JF; Siret N; Wipliez M; Palumbo F; Raffo L
A coarse-grained reconfigurable approach for low-power spike sorting architectures 2013 Carta N; Sau C; Pani D; Palumbo F; Raffo L Institute of Electrical and Electronics Engineers (IEEE)
Profiling of Dataflow-Based Coarse-Grained Reconfigurable Platforms 2013 Sau C; Palumbo F; Raffo L
DSE and profiling of multi-context coarse-grained reconfigurable systems 2013 Palumbo F; Sau C; Raffo L IEEE
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units 2014 Sau C; Palumbo F IEEE
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case 2014 Sau C; Raffo L; Palumbo F; Bezati E; Casale-Brunet S; Mattavelli M IEEE

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